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关键词： Heterojunction   TFET   High-k dielectric material   Static random access memory   SRAM   Subthreshold swing   Static noise margin   I-ON/I-OFF ratio   RF performance   FIELD-EFFECT TRANSISTORS   GALLIUM ANTIMONIDE   TUNNEL FET   TFET   MOSFET   POWER   GE  

摘要： This study introduces a novel double-dielectric Si/GaSb heterojunction TFET, incorporating III-V material in the pockets and source region to enhance band-to-band tunneling. Utilizing a high-kappa dielectric in conjunction with Si O-2 as a gate oxide, the proposed TFET demonstrates notable advancements, including an 81% reduction in OFF-current and a substantial 1.58-decade enhancement in ON-current. However, a moderate 30% increase in the average subthreshold swing is observed compared to the referenced pocket-based GaSb/Si VTFET. The RF characteristics reveal a significant 1.62-decade increase in transconductance and a 1.8-decade increase in output conductance, coupled with impressive cut-off frequency and gain-bandwidth product relative to the same reference. Additionally, the study implements a 7T SRAM cell at the device-to-circuit level through a lookup table-based Verilog-A methodology. It showcases higher noise margins and lower delays, rendering it suitable for ultra-low voltage applications requiring high-speed performance and enhanced stability.

关键词： Multi-fin FinFET   Non-quasi-static   Y-parameters   Small-signal model   Parasitics   PERFORMANCE   MOSFET   RELIABILITY   EXTRACTION   DEVICE  

摘要： Non-quasi-static small-signal models are essential for exploring the high-frequency (HF) behavior of the FinFET. In this paper, we propose a modified small-signal model for a multi-fin (MF) FinFET to extract the intrinsic and extrinsic parameters using Y-parameters extracted from TCAD. The gate resistance plays a significant role in optimizing the HF behavior with the varying numbers of fins in the MF configuration. We also test the model's accuracy with increasing temperature up to 425 K. Using well-calibrated TCAD models, we further analyze the analog and linearity figures of merit, including cutoff frequency (f(T)), the maximum frequency of oscillation (f(max)), transconductance (g(m)) and higher-order derivatives such as g(m2), g(m3), VIP2, and VIP3. Thus, the behavior of intrinsic and extrinsic parasitic resistance and capacitance is worth exploring to determine the device operation in the frequency range of >100 GHz.

关键词： Self-heating effect   Raised buried oxide   Analog   RF applicability   Temperature and interface trap concentrations   FIELD-EFFECT TRANSISTORS   NEGATIVE-CAPACITANCE   SOI   SIMULATION   MOSFET  

摘要： The self-heating effect of the silicon-on-insulator (SOI)-raised-buried-oxide (RBOX) ferroelectric tunnel field effect transistor is explored in this article. Proposed device reliability issues have been examined by activating the acceptor and donor uniform and Gaussian interface trap concentrations (ITCs). The proposed TFET is designed to diminish the ambipolar current, intensify on-state current and to improve subthreshold slope. The device performance for Analog/RF applicability is also tested by calculating the capacitances (Cgg-3.6 x 10-16 F/mu m), transconductance in the order of 7.3 x 10-3S/mu m, the cutoff frequency of 71 THz, and further transistor frequency product of 3.1 x 1015 Hz/V, transit time (1.4 x 10-15 s), and gain-bandwidth product of 12 THz are determined. All these parameter variations are investigated by changing the temperature and trap concentrations. The parameters have been compared with the room temperature and noticed an improved performance in terms of Analog/RF applicability. In addition, the introduction of the trap concentrations at the interfaces such as front gate oxide/silicon and the silicon/buried oxide is compared with no trap concentrations. It is proven that for Analog/RF applications, the proposed SOI-RBOX-ferroelectric-TFET exhibits the prominent behavior.

关键词： Junctionless   oxygen gas sensor   gate-all-around   gate stack   nanowire field-effect transistor   WORK FUNCTION   HIGH-K   SENSOR   PERFORMANCE   DIELECTRICS   MOSFET  

摘要： The design and analysis of a gate stack gate-all-around junctionless nanowire field-effect transistor (GAA-JL-NWFET) with a catalytic metal as gate contact for oxygen gas sensing is presented in this study. An n-channel GAA-JL-NWFET design using gold (Au) as the gate metal electrode is employed for oxygen sensing by utilizing appropriate work function values, which interact with oxygen gas and change the device's electrical properties. This work focuses on changes in temperature (300-500 K) and Au metal gate work function (5.05-5.20 eV) to investigate the presence of oxygen molecules and their impact on the GAA-JL-NWFET gas sensor performance. Changes in the surface potential, threshold voltage, hole concentration, electron concentration, subthreshold voltage, electric field, and drain current using the ATLAS TCAD simulator are investigated for the adsorption of gas molecules to determine the electrical characteristics of the proposed device. Changes in threshold voltage (Vth), switching ratio, and subthreshold current sensitivity (SIOFF\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$S_{{I_{{{\text{OFF}}}} }}$$\end{document}) can be considered as sensitivity parameters for sensing oxygen gas molecules. The results reveal that as the Au work function shifts at the gate by 100 mV, the sensitivity (SIOFF\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$S_{{I_{{{\text{OFF}}}} }}$$\end{document}) enhancement using gate stack GAA-JL-NWFET-based oxygen gas sensors compared to GAA-MOSFET and conventional MOSFET are 15.13% and 88.31%, respectively. Based on our simulation results, the proposed device offers excellent se

关键词： Analytical modeling   Biosensors   Schottky barrier   Reconfigurable FET   Silicon nanowire   Spacer -engineered   FET   MOSFET  

摘要： In this work, we present a comprehensive analytical model for the Spacer-Engineered Reconfigurable Silicon Nanowire Schottky Barrier Transistor (SE R-Si NW SBT) for biosensing applications. This device operates in both n-mode and p-mode configurations by incorporating dual gates located near the source and drain terminals. The electrostatic integrity of the device is enhanced by incorporating high-K spacers on both sides of the gate electrode, facilitating improved interaction between the gate and the Schottky barrier. The biomolecules present on the silicon dioxide layer within the underlap cavity at the channel center, significantly impact the electrostatic properties throughout the device channel, including channel surface potential, drain current, electric field, and threshold voltage. By utilizing the 2D Poisson equation, we effectively capture the behavior of these key electrostatic properties. The primary metrics for biomolecule detection in this device are the changes observed in the threshold voltage and drain current. Furthermore, the variations in threshold voltage are analyzed to evaluate the sensitivity of the proposed biosensor and compared with that of state-of-the-art FET-based biosensors. The reliability of our analytical approach is validated using a virtual model of the proposed biosensor and performing simulations using the Silvaco TCAD device simulation tool. Through a meticulous comparison of our analytical findings with the simulated results, we establish the accuracy and dependability of our model.

关键词： Threshold voltage  

摘要： This paper proposed an 8 nm N-type Double Gate MOSFET with improved characteristics. A comparative study has been done based on substrate and oxide material. The substrate and oxide material combination is Si-SiO2, SiGe-HfO2. This study discussed about which channel and oxide material is performed with better efficiency in sub-micron dimension in terms of Ioff, Ion, Ion/Ioff, Threshold Voltage (Vth), Sub-threshold Swing (SS) and Drain-Induced-Barrier-Lowering (DIBL) to obtain energy efficient and high performance circuits. All parameters are validated according to the IRDS-2020 and compare with existing literature. Based on improved performance SiGe material has been chosen for circuit level applications. In this research all the basic gates (NOT, AND, OR, XOR, XNOR) as well as universal gates (NAND, NOR) along with their performance with respect to Propagation Delay, Short Circuit power dissipation, Dynamic power dissipation, Power Delay Product (PDP), Energy Delay Product (EDP) and Noise Margin have been explored at 1 Volt supply voltage. These findings suggest that the proposed device is a suitable candidate to design high speed and low power logic circuits.

关键词： SiC   MOSFET   DMOSFET   Subthreshold   Short channel effect   Interface state   I-V   TRANSITION-METAL DICHALCOGENIDE   SHORT-CHANNEL   THRESHOLD VOLTAGE   ACCUMULATION   BULK  

摘要： In this article, an analytical I-V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson's equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on the fact that channel current formation mechanism of DMOSFETs is similar to that of planar MOSFETs. Comparative analysis of our model calculations with two-dimensional numerical simulation software reveals that our model exhibits a high degree of agreement in the case of planar MOSFETs and DMOSFETs. Interface traps were also considered in our analytical model, which agrees well with experimental data published elsewhere. Furthermore, the model retains a certain degree of accuracy and predictive capability even in the presence of short -channel effect. Our subthreshold model becomes complementary to existing models which only describe the I-V characteristics of SiC MOSFETs when the transistors operate above the threshold voltages.

关键词： MOSFET devices  

摘要： This paper presents a comprehensive survey of voltage balancing techniques for series-connected SiC-MOSFETs. The concept of connecting power devices in series is appealing due to the potential to achieve higher block voltages using lower-voltage components. However, this approach comes with several challenges, particularly the uneven distribution of switching transitions among these power devices, which can lead to voltage balancing problems. In addition to presenting the factors that can influence the voltage balancing across the power devices, this work introduces the main existing voltage balancing techniques proposed to improve the voltage-sharing performance of series-connected SiC-MOSFETs. © 2023 The Author(s)

关键词： Memristor emulator circuit   MOSFET   Pinched hysteresis loop   Logic circuits  

摘要： In this research article, we propose a passive two -terminal floating memristor emulator circuit (MEC). The proposed MEC consists of two NMOS transistors, one PMOS transistor and one capacitor. The MEC has a simple circuit topology structure and is more advantageous for integration, which has a chip area of only 218.04 mu m 2 . The circuit can operate without additional bias and performs well in the high frequency environment at 50 MHz. Some of the memristor's characteristics, such as pinched hysteresis loop and non -volatility, are verified using the Cadence Virtuoso environment with 0.18 mu m SMIC technology. The MEC has also been successfully proven to be effective and reliable through the temperature variation, process corner variation and Monte Carlo analysis. In addition, we built a circuit for experimental testing by using the CD4007s to verify the theoretical and simulated results. Finally, the proposed memristor emulator circuit is applied to logic circuits.

关键词： VIP   SS   DMG   SCE   TGF   PERFORMANCE   MOSFET   EXTRACTION   IMPACT  

摘要： A newly invented structure called Multi-Fin-based FinFET (M-FinFET) device is a promising candidate for future improvisation of the semiconductor industry. In this article, Multi-channel FinFET (M-ch-FinFET) is proposed. A comparative investigation of various DC, analog/linearity attributes is studied for gate length variation and oxide thickness through a Sentaurus TCAD tool. The simulation study concluded that the increased number of channels (= 3no.) has enhanced I-ON by 409.71% compared to single-channel FinFET. The decreased value of Fin width and Fin height has shown an impressive improvement of sub-threshold swing (SS) and leakage current, which helps achieve a better switching ratio. M-ch-FinFET device with lower oxide thickness (T-ox=1 nm) enhances the transconductance (G(m)), drain conductance (G(d)), intrinsic gain (A(v)), and transconductance gain factor (TGF) by 52.42%, 41.17%, 85.03%, respectively. Various linearity parameters like higher-order harmonics (G(m2) and G(m3)), voltage intercepts points (VIP2 and VIP3), and 1-dB compression point has improved by 32.32%, 110.71% 77%, 60.09%, 418.86%, 411.5% respectively gate length of 10 nm. Besides that, a symmetric dual spacer material is introduced to the proposed structure to analyze the importance of spacer engineering. The simulation study reveals that the M-ch-FinFET device with HfO2 spacer has improved driving current by 21.42%. The optimization of various short channel effects (SCEs) such as threshold voltage roll-off, sub-threshold swing (SS), and leakage current is reflected in introducing HfO2 spacer material. This detailed study is expected to design low-power RF circuits that would benefit future CMOS technology.