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关键词： 目标探测   距离估计   消频散变换   波导不变量   功率谱密度  

摘要： 浅海中传播的低频声波具有多模态特征和频散效应。对接收声信号消频散变换(DDT)可以消除频散效应,实现被动估计声源距离。针对消频散变换存在的测距多值问题,该文提出一种利用功率谱密度消频散变换的被动测距方法(PSD-DDT)。首先使用声场模型KRAKEN计算模态的水平波数;其次在只知道波导不变量大概范围的情况下,估计两个模态之间的频散常数;然后对保留了模态间干涉项的功率谱密度进行消频散变换;最后获得目标距离的估计值为PSD-DDT极大值对应的自变量与频散常数的比值。另外,当海洋参数未知时,需要分别对待测声源和引导声源进行PSD-DDT,利用自变量的比值确定声源距离,这种方法不需要估计频散常数。通过仿真和海试验证了PSD-DDT方法被动测距的有效性,并分析了波导不变量、模态阶数、噪声等因素对距离估计结果的影响。基于黄海试验结果,与DDT方法相比,PSD-DDT的测距误差下降了约49.2%。在35 km范围内最优波导不变量对应的平均相对误差约2.55%,被动测距精度较高。

关键词： Trap charges   Schottky barrier   High-k dielectric materials   Tunneling   TUNNEL FET   IMPACT   SUPPRESSION   MOSFET   FIELD   TFET  

摘要： This article mainly focuses on the impact on interface trap charges (ITCs) on dual gate source-drain Schottky barrier tunnel field effect transistor (D-G-S-D-STFET) using a high-k dielectric material. Here the high-k material raises the coupling capacitance between the channel and the gate electrode, therefore increases the charge concentration more than a conventional device because of the additional dual-source region. A higher Ion/Ioff current ratio and a reduced off-state leakage are obtained in the design of D-G-S-D-STFET. Moreover, the comparison of the D-G-S-D-STFET device is made with both the dual-metal gate TFET and conventional STFET. Further, the DC and analog/RF performances are characterized by Silvaco TCAD in terms of transfer characteristics (ID-VGS), cut-off frequency (fT), transconductance (gm), gain bandwidth product (GBP), transconductance generation factor (TGF), and transconductance frequency product (TFP). Comparatively to the conventional structures at a gate length of 40 nm has been observed that the Cut-off Frequency (fT) and the TGF are increased in the proposed device to 60 GHz and 259 V-1 range respectively with the positive and negative trap charges. Hence, the results verify that the D-G-S-D-STFET is more suitable for high-frequency applications.

关键词： SiC trench MOSFET   Self-clamped P -Shield   Turn-off loss   Switching oscillation   ELECTRIC-FIELD   SIC TRENCH   UMOSFET  

摘要： A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When VDS is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (CGD). As VDS increases, the LP region is gradually depleted, causing the Pshield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(VSurge). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better EOFF-VSurge trade-off.

关键词： DM CGAA   JL   IM   SiNW   NEGF   I-D   COMPACT EXPLICIT MODEL   PART I   DESIGN   TRANSISTOR   STACK   DIELECTRICS   IMPACT   SPACER   FINFET   FET  

摘要： Present work investigates the DC and Analog/RF characteristics such as the drain current (I-D), Transconductance (g(m)), Transconductance Generation Factor (TGF), Cut-off frequency (f(T)), Frequency Transconductance Product (FTP), Transit time (tau), and the total resistance of the source region, drain region, and channel resistance (RSD+CH) for Dual Metal (DM) Inversion Mode (IM) and Junctionless (JL) Cylindrical Gate All Around (CGAA) Silicon nanowire (SiNW) MOSFETs with 5 nm gate length using Silvaco ATLAS 3D TCAD. In this work, the Non-Equilibrium Green's Function approach along with the self-consistent solution of Schrodinger's equation and Poisson's equation has been considered. The channel is taken to be lightly doped in the case of IM DM CGAA SiNW type of device. The effect of DM Gate work function engineering for SiNW channel of diameter 3 nm with gate oxide (SiO2) the thickness of 0.8 nm on I-D,g(m), TGF, f(T), tau, FTP and R-CH has been studied. Moreover, a comparative study has been made between IMDM and JLDM CGAA SiNW devices with the above-mentioned parameters. For the JL device, the optimization of doping concentration is performed to get the same (i) I-ON current and (ii) threshold voltage (V-TH) as the IM device. About 3.09 times and 21.89 times reduction in I-OFF is seen for the same I-ON and V-TH optimized devices respectively as compared to IM device. It has been found that DM Gate variation minimizes drain-induced barrier lowering (DIBL) in IM and JL devices. The JL SiNW showed much lower DIBL similar to 16.46 mV/V, a near ideal SS similar to 60 mV/dec, and higher I-ON/I-OFF current ratio similar to 7.04 x 10(8) which is much better as compared to those reported in the literature for cylindrical gate all around (CGAA) devices. Also, it is found that the JL SiNW device performs better than IM in terms of SS, DIBL, I-ON/I-OFF, g(m), TGF, f(T), tau, FTP and RSD+CH.

关键词： Total ionizing dose   Single event gate rupture   Synergistic effect   VDMOS with stacked layers   TCAD simulation   POWER MOSFETS   SEGR FAILURE   DEGRADATION   IMPACT   MODEL  

摘要： The synergistic effect of total ionizing dose on single event gate rupture (SEGR) was simulated in the vertical double diffusion metal oxide semiconductor device with SiO2-Si3N4 stacked gate layer. In comparison to the device with a single SiO2 gate layer, the synergistic effect was revealed to be suppressed in the device with SiO2-Si3N4 stacked layer. The mechanism is that the oxide layer is a sensitive area of the SEGR effect. Compared with the single SiO2 layer, the superposition of the additional electric field formed by the trapped holes in the sensitive area of the stacked layer leads to a decrease in the sensitivity of the synergistic effect, which is more obvious with increasing the volume of the Si3N4 layer.

关键词： Nongray model   Multi-speed phonon lattice Boltzmann method   Phonon ballistic transport   GaN HEMTs   SPREADING RESISTANCE   TRANSPORT   TEMPERATURE   CONDUCTION   EQUATION   IMPACT   MOSFET  

摘要： Gallium Nitride (GaN) high electron mobility transistors (HEMTs) exhibit superior electrical properties for power and radio frequency applications, but performance is compromised by localized Joule heating, increasing channel temperatures. Precise thermal analysis during design is essential for optimizing device architecture and management strategies. Traditional methods like the Fourier heat diffusion equation (HDE) and the phonon lattice Boltzmann method (PLBM) with the D2Q8 scheme inadequately model phonon ballistic transport at high Knudsen numbers. This study introduces a nongray multi-speed PLBM integrated with the drift-diffusion model to analyze electro-thermal processes in GaN HEMTs. Validated through simulations of thermal conductivities in two-dimensional GaN thin films, the approach examines internal temperature rise in GaN HEMTs under different gate voltages, comparing results with HDE and gray BTE models, and emphasizing the need for non-Fourier effects in thermal analysis. It also evaluates the impact of GaN layer thickness on temperature distribution, providing a robust solution for thermal analysis in GaN HEMTs and other field-effect transistors.

关键词： Junctionless transistor   Gate-all-around (GAA)   Nanowire   Through-silicon via (TSV)   THROUGH-SILICON   CIRCUIT PERFORMANCE   CMOS   IMPACT   MOSFET  

摘要： This paper presents a novel structure of TSV-based silicon nanotube gate-all-around FETs (both junction-based and junctionless) along with their electrical characteristics using Silvaco ATLAS 3D device simulator. In comparison, the junctionless silicon nanotube gate-all-around structures presented an excellent performance improvement over the junction-based structures in terms of short channel effects, an improved drain-induced barrier lowering of similar to 28% for n-MOS and similar to 22% for p-MOS, and improved (I-ON/I-OFF) switching ratio of similar to 68% for n-MOS and similar to 42% for p-MOS. Similarly, the junctionless structure shows a steep subthreshold value very close to the ideal value (similar to 60 mv/dec). Furthermore, the static and transient characteristics of CMOS inverter circuits designed using the complementary device architecture have been explored using mixed-mode simulations. The noise margin and propagation delay of the circuit are analyzed and are found to agree with the information available in the literature for nano-scaled devices.

关键词： MOSFETs   Radiation effects   Solid-state detectors   INTERFACE-TRAP BUILDUP   CHARGE NEUTRALIZATION   RADIATION   DEPENDENCE   DOSIMETERS   SIMULATION   ELECTRONS   CENTERS   RADFET   OXIDES  

摘要： The response of commercial-off-the-shelf CD4007 p-channel MOSFET exposed to 60Co radiation under switchedbias conditions is studied by real time monitoring the threshold voltage evolution with accumulated dose. The possibility to employ switched-bias techniques to recover threshold voltage is demonstrated. As reported for other devices, non-monotonic responses are observed. A physics-based numerical model that takes into account both charge buildup within the oxide and generation of interface traps is employed to reproduce the experimental results. The implications for dosimetry are discussed.

关键词： DG-JLT   Analog/RF   Junctionless transistor   Cut-off frequency   Maximum oscillation frequency   JUNCTIONLESS TRANSISTOR   SIMULATION   MOSFET   MODEL  

摘要： Shrinking MOSFETs suffer performance hits due to short-channel effects and leakage. Junctionless transistors JLTs emerge as promising alternatives due to simpler fabrication and better gate control. This paper investigates the analog and RF performance characteristics of n-type SiliconBased Double Gate Junctionless Transistors with varying channel lengths (15 nm, 20 nm, and 25 nm) This study evaluates analog device performance through critical parameters: drain current density (Id), transconductance (gm), output resistance (RO), intrinsic gain (gmRO), and transconductance generation factor (gm/Id). These parameters assess current handling, gain characteristics, and design efficiency, providing a comprehensive analysis for analog circuit applications. Results indicate that the device having 15 nm channel length exhibits a transconductance which is 25.38 % more than the 20 nm variant and drain current which is 44.7 % more than the latter, suggesting its superior performance to devices with longer channel lengths. In addition, the RF performance of the devices is evaluated using the small signal model of the device. This work further investigates the high-frequency response of the devices using key figures of merit (FoMs): gate capacitances (Cgs, Cgd, Cgg), cut-off frequency (fT), and maximum oscillation frequency (fMAX). These parameters quantify the influence of parasitic capacitances on switching speed and the maximum useable frequency for analog and RF applications. Analyzing Cgs, Cgd, and Cgg reveals the impact of gate control on high-frequency operation. The device having 15 nm channel length, exhibits an increase of 47.29 % in fT and 68.97 % increase in fMAX compared to device having 20 nm channel length. The findings underscore the significance of channel length optimization in enhancing the Analog and RF performance of n-type Silicon-based Double Gate Junctionless Transistors.

关键词： SiC MOSFET   Modelling   Physical effects   Power electronic  

摘要： An improved semi-physical model for a SiC MOSFET incorporated with relevant physical effects and temperature characteristics is proposed based on the EKV model. A simulation analysis of the Junction Field Effect Transistor (JFET) effect, Drain Induced Barrier Lowering (DIBL) effect, channel length modulation effect, velocity saturation effect, and interface trap charge effect in SiC MOSFET devices is performed using Sentaurus TCAD. Based on the influence of physical effects on the characteristics of SiC MOSFET devices, mathematical corrections r(V-gs) and r(V-ds), which can describe the relevant physical effects, are introduced into the original EKV model. The capacitance is accurately modelled to achieve the required match between the transient characteristics of the devices. The accuracy of the model is verified by static tests and double-pulse experiments. Results show that the improved model can do a better job of simulating the actual operating conditions of the device. In addition, its accuracy and applicability are greatly improved, providing a semi-physical model with a wider range of applicability for the simulation of SiC MOSFETs in power electronic systems.